The disclosure relates in general to a switched capacitor circuit. In particular, the disclosure relates to a switched capacitor circuit using an operational amplifier with switches for receiving input signals.
An amplifier typically has an input and an output. The amplifier amplifies a signal applied to the input and provides the amplified signal to the output. In general, amplifiers are characterized by the amount of gain or amplification provided, bandwidth or frequency of operation, noise characteristics, and accuracy of amplification. Amplifiers are commonly used in many different types of circuits, for example, analog to digital converters (ADC).
One type of amplifier is a switched capacitor amplifier. A switched capacitor amplifier is a clocked circuit that operates in discrete steps. For example, in a first phase of a clock cycle a voltage is sampled, in particular, capacitors of a switched capacitor amplification stage are charged to the voltage. Switches are used to couple the capacitors in different configurations. The switches are transmission gates formed from complementary transistor types. In a second phase of a clock cycle, the capacitors of the switched capacitor amplifier are coupled via switches around an amplifier in a configuration to amplify a sampled voltage. The voltages stored on the capacitors in the first phase of the clock cycle determine the magnitude of an output voltage of the amplification stage. The gain is typically fixed by the amplification stage configuration (in the second phase of the clock cycle) and the capacitor values.
Multi-stage pipelined analog to digital converters (ADC) provide efficient high speed conversion of analog signals to digital equivalents. A representative multi-stage pipelined ADC 10 is shown in FIG. 1. The ADC 10 generally includes a plurality of converter stages, such as stages 11, 12 and 13, arranged in series relative to each other. Each converter stage operates by comparing an analog input voltage to thresholds provided by reference signals Vretp and Vrefn. As a result, each converter stage provides one or more bits of digital data to a digital correction circuit 15. The digital correction circuit 15, in turn, resolves the digital output from each stage into a digital output 16 that corresponds to an analog input 17.
FIG. 2 is a generalized block diagram of each converter stage. In operation, each stage accepts an analog input voltage and generates a residual analog voltage and a digital stage output. In particular, each stage applies the analog input voltage to a multiplying digital to analog converter (MDAC) 19 to generate the residual analog voltage. The residual analog voltage is then provided to a comparator 18, which generates the digital stage output. The residual analog voltage also serves as input to subsequent converter stages. This arrangement is also referred to herein as a bit-and-one-half analog to digital converter.
Each stage may include an MDAC as shown in FIG. 3. The MDAC comprises a sampled and hold circuit S/H and a multiplier circuit Mux, operating in accordance with an one cycle clock with phases designated as φ1 and φ2. During a sampling phase φ1, wherein the switches labeled φ1 are closed, sampled and hold circuit S/H samples input voltage Vin. During a subsequent integration phase φ2, wherein the switches labeled φ2 are closed, multiplier circuit Mux amplifies the sampled voltage. The gain of multiplier circuit Mux is set here as two, as an example. Reference voltage (Vref) is either added to or subtracted from the amplified voltage depending on the comparison results. A resulting output voltage (2×Vin±Vref) is then applied to a next amplification stage and the process is repeated such that the sample voltage is pipelined to determine the remaining digital bits sequentially as is well known.
However, MDAC shown in FIG. 3 outputs data when phases φ1 and φ2 are completed, decreasing data transmission efficiency. In addition, MDAC requires two operational amplifiers, consuming power and cost.
FIG. 4 shows another conventional switched capacitor circuit as disclosed in U.S. Pat. No. 5,574,457 to Garrity et al.
MDAC circuit 20 has an input A, an input B, an input VREFMA, an input VREFMB, an input VREFPA, an input VREFPB, an output A, and an output B.
Capacitors C11˜C14 and switches coupled thereto correspond to a first sampling circuit for an amplifier 22. Capacitors C11 and C12 receive a voltage from input A. Capacitors C13 and C14 receive a voltage from input B. The voltage difference between input A and B is amplified by an amplifier 22. Capacitors C15˜C18 and switches coupled thereto correspond to a second sampling circuit for amplifier 22. Capacitors C15 and C16 receive a voltage from input A. Capacitors C17 and C18 receive a voltage at input B. Capacitors C11˜C14 are charged to a voltage (between inputs A and B, and ground) during a first clock phase φ1 while capacitors C15˜C18 are coupled around amplifier 22 in a gain configuration, wherein the switches labeled by φ1 are turned on. A differential reference voltage is applied across inputs VREFPA and VREFPB. During a second clock phase φ2, capacitors C15˜C18 are charged to a voltage (between inputs A and B, and ground) while capacitors C11˜C14 are coupled around amplifier 22 in a gain configuration, wherein the switches labeled by φ2 are closed. A differential reference voltage is applied across inputs VREFMA and VREFMB. Amplifier 22 is operated throughout the clock cycle due to the double sampling process, improving data transmission speed and reducing power.
However, the switches (labeled 24A˜24D) connected to the input terminal and inverting input terminal of amplifier 22 comprise resistance, decreasing the operating of amplifier 22.